The present invention relates generally to complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus, and more particularly, relates to a high performance., low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
Various arrangements have been proposed to overcome some of the problems with partially depleted SOI technology. One of the more pronounced problems observed in partially depleted SOI technology is the degraded cell stability. This degraded cell stability is caused by half selected cell disturb sensitivity. With excessive N-channel field effect transistor (NFET) body charge accumulation and uncontrollably low Vt in the access transistor of an SOI RAM cell, the SOI RAM cell content may be unintentionally overwritten under a half-selected condition; that is when it is adjacent to a currently selected cell on the same word line.
A need exists for a high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus.
A principal object of the present invention is to provide a high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus. Other important objects of the present invention are to provide such high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus are provided. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier includes a precharge circuit for charging complementary data lines to a predefined precharge voltage during a precharge cycle. The precharge voltage is lower than a full rail voltage. A pre-amplifying mechanism produces an offset voltage between the complementary data lines before the sense amplifier is set.
In accordance with features of the invention, the pre-amplifying mechanism includes a pre-amplifying FET that is substantially smaller than a sensing silicon-on-insulator (SOI) FET in the sense amplifier. The full rail voltage is provided for the complementary data lines when the sense amplifier is set. The full rail voltage can be applied during the write mode.